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[Other resourceGame_HLD3

Description: 基于fpga和xinlinx ise的小游戏的vhdl程序,希望对你有所帮助!-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
Platform: | Size: 986916 | Author: 王萌 | Hits:

[VHDL-FPGA-VerilogGame_HLD3

Description: 基于fpga和xinlinx ise的小游戏的vhdl程序,希望对你有所帮助!-xinlinx and they simply based on the small game and ideally the VHDL process, and I hope to help you!
Platform: | Size: 987136 | Author: 王萌 | Hits:

[VHDL-FPGA-Verilog一些VHDL源代码

Description: 内有波形发生器,加法器,经典双进程状态机,伪随机熟产生器,相应加法器的测试向量,16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45056 | Author: 蔡孟颖 | Hits:

[SCMVHDL实现简单的8位CPU2

Description: 用VHDL实现8位的单片机!里面 有开发过程和代码阿!很详细的哦-using VHDL eight of SCM! Inside the development process and code Ah! Detailed oh
Platform: | Size: 53248 | Author: 冯海 | Hits:

[VHDL-FPGA-VerilogMPSK调制与解调VHDL程序与仿真

Description: MPSK调制与解调VHDL程序与仿真,具有很高的参考价值!!vhdl代码!-MPSK modulation and demodulation process and VHDL simulation, high reference value! ! VHDL code!
Platform: | Size: 79872 | Author: 温暖感 | Hits:

[VHDL-FPGA-Verilog44vhdl

Description: 44个vhdl实例 注1: 含有不可综合语句,请自行修改 注2: 一些PLD只允许I/O口对外三态,不支持内部三态,使用时要注意 注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件,并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I/O external three states, do not support the internal three-state, the use of attention to Note 3 : Design RAM is the best way to use devices provide manufacturers with the software automatically generating RAM components, and the VHDL process cases of
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[VHDL-FPGA-VerilogVHDL_processor

Description: 利用VHDL语言描述的一个简单微处理器,可以通过修改源码来调整指令集,可以在Quartus II上直接运行和编译.-use VHDL description of a simple microprocessor, can modify the source codes to adjust instruction set, Quartus II can be directly compiled and running.
Platform: | Size: 742400 | Author: 赵康 | Hits:

[VHDL-FPGA-VerilogNCO_ip

Description: NCO的VHDL程序,是利用IP核生成的,超好的,快下吧-NCO of the VHDL process is the use of nuclear-generated IP, super good, fast, are you
Platform: | Size: 128000 | Author: 张俊 | Hits:

[VHDL-FPGA-Verilogla_usb-SPISRAM

Description: 有关到SRAM的VHDL程序,也涉及到USB接口,希望对大家有所帮助-Related to the SRAM of the VHDL process involves the USB interface, and they hope to help everyone
Platform: | Size: 2048 | Author: 李锐 | Hits:

[VHDL-FPGA-VerilogCOUNT10

Description: 一个十进制计数器的vhdl程序,大家可以参考,已经经过编译了-A decimal counter VHDL process, everyone can refer to, has been compiled
Platform: | Size: 108544 | Author: wangyan | Hits:

[VHDL-FPGA-Verilogstep_motor

Description: 步进电机定位控制系统VHDL程序,可以进行步进角的倍数设定,激磁方式的选择-Stepper motor positioning control system for VHDL process can be carried out in multiples of step angle setting, the choice of excitation mode
Platform: | Size: 4096 | Author: wavy | Hits:

[source in ebookvhdlshili

Description: 北京邮电大学的经典教材,内含很多经典的vhdl的程序实例,是很好的参考资料-Beijing University of Posts and Telecommunications of the classic material, including many classic examples of VHDL process is a very good reference
Platform: | Size: 2980864 | Author: 蝈蝈 | Hits:

[VHDL-FPGA-VerilogVHDL

Description: 实现一个10秒倒计时电路,要求使用8*8点阵显示计时结果。在QuartusII平台上设计程序和仿真题目要求,并下载到实验板验证实验结果。-Achieve a 10-second countdown circuit, requires the use of 8* 8 dot matrix display timing results. QuartusII platform in the design process and simulation on the subject request and download to the board to verify the experimental results.
Platform: | Size: 404480 | Author: li | Hits:

[Software EngineeringVHDL

Description: 在电子技术中,频率是最基本的参数之一,又与许多电参量的测量方案、测量结果都有十分密切的关系,因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速,以及便于实现测量过程自动化等优点,是频率测量的重要手段之一。在本次毕业设计中我们选择使用单片机来制作数字频率计,并在实际制作中采用了直接测频法。利用延时产生的时基门控信号来控制闸门,通过在单位时间内计数器记录下的脉冲个数计算出输入信号的频率,最终送入LCD中显示。这样制作出来的频率计不仅可以满足设计题目的参数要求,而且具有了单片机的稳定性和成熟性,且控制能力强,是一种低成本,高可靠的设计方案。-In electronic technology, the frequency is one of the most basic parameters, but also with a number of electrical parameters of the measurement program, the measurement results have a very close relationship between the frequency of measurement, therefore it is even more important. Measurement of the frequency of a number of means, electronic measurement of the frequency counter with high precision, easy to use, rapid measurement, and measurement is easy to realize the advantages of process automation is an important means of measuring the frequency of one. Graduates in this design we have chosen to make use of single-chip digital frequency meter, and used in the actual production of a direct frequency measurement method. Delay arising from the use of gated time-base signal to control the gate time in units of the pulse counter to record the number of calculated frequency of the input signal, and ultimately into the LCD display. This produced not only the frequency of the parameters to
Platform: | Size: 220160 | Author: 张林锋 | Hits:

[VHDL-FPGA-VerilogVHDL

Description: VHDL语法入门 1.1 VHDL程序构件 1.2 文法规则 1.3 数据对象及类型 1.4 运算符与表达式 1.5 VHDL语句 1.6 进程与子程序 1.7 资源库与程序包-Introduction to VHDL syntax 1.2 Component 1.1 VHDL procedures grammar rules and type of data object 1.3 Operators 1.4 and 1.6 Expression 1.5 VHDL process statement with the subprogram 1.7 Resource Library with the package
Platform: | Size: 21504 | Author: 王强 | Hits:

[VHDL-FPGA-Verilogvhdl

Description: 哈工大的VHDL课件,对于学习VHDL语言是个非常不错的教材,讲的非常详细,还有一些VHDL的经典例子,和分析。介绍了VHDL在实际中的应用和开发流程。-HIT courseware of VHDL, VHDL language learning is a very good teaching material, talking about a very detailed, there are some classic examples of VHDL, and analysis. Described in VHDL in the actual application and development process.
Platform: | Size: 282624 | Author: 但的东 | Hits:

[VHDL-FPGA-Verilog17869318fpga-example1

Description: FPGA实例包含UARTverilog TLC7524接口电路程序 TLC5510 VHDL控制程序 DAC0832 接口电路程序 LCD控制VHDL程序与仿真等-FPGA interface circuit examples include UARTverilog TLC7524 TLC5510 VHDL process control procedures procedures DAC0832 LCD control interface circuit and simulation of VHDL procedures and so on
Platform: | Size: 66560 | Author: yang | Hits:

[VHDL-FPGA-VerilogVHDLProgramingLearn

Description: VHDL编程心得体会 包括进程、时钟、变量信号等应该注意的地方-VHDL process、Timer、signal and other things that is easy make mistake
Platform: | Size: 107520 | Author: happsky | Hits:

[VHDL-FPGA-VerilogVHDL-3BCD

Description: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来,这里采用动态分时总线切换电路对数码管进行扫描,对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Platform: | Size: 56320 | Author: will li | Hits:

[File FormatVHDL

Description: VHDL相关的知识,说明了在学习VHDL过程中长出现的一下问题,是很好的材料。-VHDL knowledge, long learning VHDL process of what is a very good material.
Platform: | Size: 1188864 | Author: 郭天圣 | Hits:
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